Products » EDA Software » IDesignSpec
TM
IDesignSpecTM
: The Fastest Path to Code from Register Specification
IDesignSpecTM (IDS) is an engineering tool that allows a chip or
system designer to create the register map specification once and automatically generate
all possible views from it. Various outputs are possible such as OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. Using IDS improves design quality and improves engineers' productivity.
Key Features
- Easy to use Plugin for all popular Editors. Does not require any
new language to be learnt.
- Transformations possible out of the box:
- Verilog, VHDL synthesizable design code for industry standard bus protocols (AMBA-AHB, AVALON, and Proprietary)
- Test bench files for OVM and VMM
- C header files, and C++ Class files for Firmware and Device Drivers
- HTML and PDF documentation
- SystemC, SystemVerilog based Verification code (based on OVM and VMM methodology)
- IP-XACT output conforming to
Spirit Consortium
- SystemRDL standard output
- Read in : IP-XACT, XML, CSV
- Register data stored in native editor format, not locked to Agnisys.
- Extensible: User defined transformations are possible.
Key Benefits
- Automate register data management.
- Improves the design process: "Write once, use everywhere".
- Supports Architecture, Design, Verification, Diagnostics, Firmware, Application
Software and Documentation groups.
Unique customer engagement model
Agnisys has a unique engagement model, in that its support team helps the customer bring their existing register specs into IDesignSpec. It creates Tcl or XSLT scripts to create the exact output that works in the customer’s existing flow. Without spending much time customers are able to evaluate the tool and the improved work flow. Customers are not locked into the Agnisys file format since the files are stored in the native document editor, under complete control of the user.
For a short web based demo please contact: